The present invention relates to a layout structure of a semiconductor integrated circuit effective in improving the accuracy of the interconnect pattern dimensions.
With increasing reduction in interconnect width due to device miniaturization, the variation in interconnect width caused by an optical proximity effect is becoming non-negligible. The optical proximity effect is a phenomenon that the finished value of the width of a given interconnect varies with the distance from the given interconnect to a nearby interconnect. The optical proximity effect causes degradation of the accuracy of the interconnect dimensions. Therefore, depending on the interconnect spacing, the interconnect width may possibly become smaller than a specified value, and in some cases, even be broken, under the influence of the optical proximity effect.
Under the circumstances described above, correction for an influence of the optical proximity effect, or optical proximity effect correction (OPC), is indispensable. The OPC is a technique in which a variation of the interconnect width occurring depending on the interconnect spacing is predicted, and correction is made to cancel the variation, to thereby keep the finished interconnect uniform.
For example, a technique disclosed in Patent Document 1 is known for measures taken for polysilicon interconnects.
Patent Document 1: Japanese Laid-Open Patent Publication No. 10-32253